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data sheet ics810001dk-21 revision b april 13, 2010 1 ?2010 integrated device technology, inc. femtoclock? dual vcxo video pll ICS810001-21 general description the ICS810001-21 is a pll based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. the device contains two internal frequency multiplication stages that are cascaded in series . the first stage is a vcxo pll that is optimized to provide reference clock jitter attenuation, and to support the complex pll multiplication ratios needed for video rate conversion. the second stage is a femtoclock? frequency multiplier that provides the low jitter, high frequency video output clock. preset multiplication ratios are sele cted from internal lookup tables using device input selection pins. the multiplication ratios are optimized to support most common video rates used in professional video system applications. the vcxo requires the use of an external, inexpensive pullable crystal. two crystal connections are provided (pin selectable) so that both 60 and 59.94 base frame rates can be supported. the vcxo require s external passive loop filter components which are used to set the pll loop bandwidth and damping characteristics. features ? jitter attenuation and frequency translation of video clock signals ? supports smpte 292m, itu-r rec. 601/656 and mpeg-transport clocks ? support of high-definition (hd) and standard-definition (sd) pixel rates ? dual vcxo-pll supports both 60 and 59.94hz base frame rates in one device ? supports both 1000/1001 and 1001/1000 rate conversions ? dual pll mode for high-frequency clock generation (36mhz to 148.5mhz) ? vcxo-pll mode for low-frequency clock generation (27mhz and 26.973mhz) ? one lvcmos/lvttl clock output ? two selectable lvcmos/lvttl clock inputs ? lvcmos/lvttl compatible control signals ? rms phase jitter @148.351 6mhz, (12khz - 20mhz): 1.089ps (typical) ? 3.3v supply voltage ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages supported input frequencies supported output frequencies hiperclocks? ic s f vcxo = 27mhz f vcxo = 26.973mhz 27.0000mhz 26.9730mhz 27.0270mhz 27.0000mhz 74.1758mhz 74.1016mhz 74.3243mhz 74.2499mhz 74.2500mhz 74.1758mhz 27.0270mhz 27.0000mhz 26.9730mhz 26.9461mhz 74.1758mhz 74.1016khz 45.0000khz 44.9550khz 33.7500khz 33.7163khz 15.6250khz 15.6094khz 15.7343khz 15.7185khz 28.1250khz 28.0969khz f vcxo = 27mhz f vcxo = 26.973mhz 148.5000mhz 148.3515mhz 74.2500mhz 74.1758mhz 49.5000mhz 49.4505mhz 33.0000mhz 32.9670mhz 162.0000mhz 161.8380mhz 81.0000mhz 80.9190mhz 54.0000mhz 53.9460mhz 36.0000mhz 35.9640mhz 27.0000mhz 26.9730mhz
ics810001dk-21 revision b april 13, 2010 2 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll block diagram pin assignment charge pump vcxo v3:v0 phase detector q output divider 00 = 4 (default) 01 = 8 10 = 12 11 = 18 vcxo feedback divider (m value from table) vcxo input pre-divider (p value from table) vcxo jitter attenuation pll xtal_in0 xt al_out0 xtal_ in1 xtal_out1 lf1 lf0 iset loop filter vcxo divider table oe xtal_sel 01 mf mr master reset 0 1 clk0 clk1 clk_sel n1:n0 4 2 11 10 10 11 01 01 10 11 00 2 nbp1:nbp0 femtoclock frequency multiplier 0= x22 (default) 1= x24 pulldown pulldown pulldown pulldown pulldown pulldown pulldown pullup pulldown pullup 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 lf1 lf0 iset v dd nbp0 gnd clk_sel clk1 n0 n1 nbp1 oe gnd q v ddo v dda clk0 v0 v dd mr mf v1 v2 v3 xtal_in0 xtal_out0 gnd xtal_in1 xtal_out1 xtal_sel v dd v ddx ICS810001-21 32 lead vfqfn 5mm x 5mm x 0.925mm package body k package top view
ics810001dk-21 revision b april 13, 2010 3 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 lf1, lf0 analog input/output loop filter connection node pins. 3 iset analog input/output charge pump current setting pin. 4, 11, 25 v dd power core supply pins. 5, 22 nbp0, nbp1 input pullup pll bypass control pins. see block diagram. 6, 20, 29 gnd power power supply ground. 7 clk_sel input pulldown input clock select. when high sele cts clk1. when low, selects clk0. lvcmos / lvttl interface levels. 8, 9 clk1, clk0 input pulldown single-ended clock inputs. lvcmos/lvttl interface levels. 10, 14, 15, 16 v0, v1, v2, v3 input pulldown vcxo pll divider selection pins. lvcmos/lvttl interface levels. 12 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the output to go low. when logic low, the internal dividers and the output is enabled. lvcmos/lvttl interface levels. 13 mf input pulldown femtoclock multiplication factor select pin. lvcmos/lvttl interface levels. 17 v dda power analog supply pin. 18 v ddo power output supply pin. 19 q output single-ended vcxo pll clock output. lvcmos/lvttl interface levels. 21 oe input pullup output enable. when logic low, the clo ck output is in high-impedance. when logic high, the output is enabled. lvcmos/lvttl interface levels. 23, 24 n1, n0 input pulldown femtoclock output divide select pins. lvcmos/lvttl interface levels. 26 xtal_sel input pulldown crystal select. when high, selects xtal1. when low, selects xtal0. lvcmos/lvttl interface levels. 27, 28 xtal_out1, xtal_in1 input crystal oscillator interf ace. xtal_in1 is the input. xtal_out1 is the output. 30, 31 xtal_out0, xtal_in0 input crystal oscillator interf ace. xtal_in0 is the input. xtal_out0 is the output. 32 v ddx power power supply pin for vcxo charge pump. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf c pd power dissipation capacitance (per output) v dd = v ddo = 3.465v 8.5 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance 22.5 ?
ics810001dk-21 revision b april 13, 2010 4 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll function tables table 3a. vcxo pll pre- and feedback divider function table input vcxo pll configuration v3 v2 v1 v0 pre-divider p feedback- divider m 0 (default) 0 (default) 0 (default) 0 (default) 1000 1000 0 0 0 1 1001 1000 0 0 1 0 11000 4004 0 0 1 1 11011 4000 0 1 0 0 11000 4000 0 1 0 1 4004 4004 0 1 1 0 4004 4000 0 1 1 1 1000 1001 1 0 0 0 250 91 1 0 0 1 253 92 1 0 1 0 92 92 1011 1 600 1100 1 800 1101 1 1728 1110 1 1716 1111 1 960
ics810001dk-21 revision b april 13, 2010 5 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll table 3b. input frequency table table 3c. output frequency table (dual pll mode) note: use the vcxo-pll mode to achieve output frequencies of 27mhz or 26.973mhz. see table 3h. input crystal frequency (f vcxo ) v3 v2 v1 v0 27mhz 26.973mhz 0 (default) 0 (default) 0 (default) 0 (default) 27.0000mhz 26.9730mhz 0 0 0 1 27.0270mhz 27.0000mhz 0 0 1 0 74.1758mhz 74.1016mhz 0 0 1 1 74.3243mhz 74.2499mhz 0 1 0 0 74.2500mhz 74.1758mhz 0 1 0 1 27.0000mhz 26.9730mhz 0 1 1 0 27.0270mhz 27.0000mhz 0 1 1 1 26.9730mhz 26.9461mhz 1 0 0 0 74.1758mhz 74.1016mhz 1 0 0 1 74.2500mhz 74.1758mhz 1 0 1 0 27.0000mhz 26.9730mhz 1 0 1 1 45.0000khz 44.9550khz 1 1 0 0 33.7500khz 33.7163khz 1 1 0 1 15.6250khz 15.6094khz 1 1 1 0 15.7343khz 15.7185khz 1 1 1 1 28.1250khz 28.0969khz f vcxo femtoclock look-up table output frequency f q (mhz) mf n1 n0 27mhz 0 0 0 148.5000 0 0 1 74.2500 0 1 0 49.5000 0 1 1 33.0000 1 0 0 162.0000 1 0 1 81.0000 1 1 0 54.0000 1 1 1 36.0000 26.973mhz 0 0 0 148.3515 0 0 1 74.1758 0 1 0 49.4505 0 1 1 32.9670 1 0 0 161.8380 1 0 1 80.9190 1 1 0 53.9460 1 1 1 35.9640
ics810001dk-21 revision b april 13, 2010 6 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll table 3d. clk_sel function table table 3e. mr master reset function table table 3f. femtoclock pll feedback divider function table table 3g. pll output divider function table table 3h. pll bypass logic function table input operation clk_sel 0 (default) selects clk0 as pll reference input. 1 selects clk1 as pll reference input. input operation mr 0 (default) normal operation, internal dividers and the output q are enabled. 1 internal dividers are reset. q output is in logic low state (with oe = 1). input operation mf 0 (default) selects mf = 22. the 2nd stage pll (femtoclock. multiplies the output frequency of the vcxo-pll by 22. 1 selects mf = 24. the 2nd stage pll (femtoclock. mu ltiplies the output frequency of the vcxo-pll by 24. input operation n1 n0 0 (default) 0 (default) output divider n = 4. 0 1 output divider n = 8. 1 0 output divider n = 12. 1 1 output divider n = 18. input operation nbp1 nbp0 00 vcxo-pll mode: the input reference frequency is divided by the pre-divider p and is multiplied by the vcxo-pll. f out = (f ref p) * m. 01 test mode: the input reference frequency is divided by the pre-divider p and the output divider n and bypasses both plls. f out = f ref (p * n). 10 femtoclock mode: the input reference frequency is divided by the pre-divider p multiplied by the 2 nd pll (femtoclock, mf). the 1 st pll (vcxo-pll, m) is bypassed. this mode does not support jitter attenuatiion. f out = (f ref p) * mf n. 1 (default) 1 (default) dual pll mode: both plls are cascaded for jit ter attenuation and frequency multiplication. f out = (f ref p) * m * mf n.
ics810001dk-21 revision b april 13, 2010 7 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = v ddx = 3.3v 5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i xtal_in other inputs 0v to v dd -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 37 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd ? 0.15 3.3 v dd v v ddo output supply voltage 3.135 3.3 3.465 v v ddx charge pump supply voltage v dd ? 0.04 3.3 3.465 v i dd power supply current 290 ma i dda analog supply current 15 ma i ddo output supply current no load 4 ma i ddx charge pump supply current 4ma
ics810001dk-21 revision b april 13, 2010 8 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll table 4b. lvcmos/lvttl dc characteristics, v dd = v ddo = v ddx = 3.3v 5%, t a = 0c to 70c ac electrical characteristics table 5. ac characteristics, v dd = v ddo = v ddx = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. see parameter measurement information section. note 1: refer to the phase noise plot. note 2: lock time measured from power-up to stable output frequency. symbol parameter test conditions minimum typical maximum units v ih input high voltage 2.0 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk[0:1], clk_sel, p[1:0], v[3:0], n[1:0], mr, mf, xtal_sel v dd = v in = 3.465v 150 a oe, nbp0, nbp1 v dd = v in = 3.465v 5 a i il input low current clk[0:1], clk_sel, p[1:0], v[3:0], n[1:0], mr, mf, xtal_sel v dd = 3.465v, v in = 0v -5 a oe, nbp0, nbp1 v dd = 3.465, v in = 0v -150 a v oh output high voltage i oh = -24ma 2.6 v v ol output low voltage i ol = 24ma 0.5 v symbol parameter test conditions minimum typical maximum units f out output frequency nbp0, nbp1 = 00 14 35 mhz nbp1 = 1 31 175 mhz t jit(?) rms phase jitter, (random), note 1 148.3516mhz, integration range: 12khz ? 20mhz 1.089 ps t r / t f output rise/fall time 20% to 80% 250 750 ps odc output duty cycle 48 52 % t lock vcxo & femtoclock pll lock time; note 2 m = 92, bandwidth = 475hz 100 ms m = 4004, bandwidth = 6hz 25 s
ics810001dk-21 revision b april 13, 2010 9 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll typical phase noise at 148.3516mhz 148.3516484mhz rms phase jitter (random) 12khz to 20mhz = 1.089ps (typical) noise power dbc hz offset frequency (hz) 10hz 100hz 1khz 10khz 100khz 1mhz 30mhz
ics810001dk-21 revision b april 13, 2010 10 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll parameter measureme nt information 3.3v output load ac test circuit output duty cycle/pulse width/period output rise/fall time phase jitter lvcmos gnd measurement point 1.65v5% -1.655% v dd , v ddo, v ddx 1.65v5% v dda t period t pw t period odc = v ddo 2 x 100% t pw q 20% 80% 80% 20% t r t f q offset frequency f 1 f 2 phase noise plot rms jitter = area under offset frequency markers noise power
ics810001dk-21 revision b april 13, 2010 11 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll applications information recommendations for unused input pins inputs: clk inputs for applications not requiring the us e of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but ca n be added for additional protection. a 1k ? resistor can be used. power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perform ance, power supply isolation is requir ed. the ICS810001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda, v ddo and v ddx should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v dda pin. figure 1. power supply filtering v dd v ddx v dda 3.3v 10 ? 10 ? 10f .01f .01f 10f .01f
ics810001dk-21 revision b april 13, 2010 12 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 2. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 2. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics810001dk-21 revision b april 13, 2010 13 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll schematic example figure 3 shows an example of the ICS810001-21 application schematic. in this example, the device is operated at v dd = v ddx = v ddo = v dda = 3.3v. the decoupling capacitors should be located as close as possible to the power pin. the input is driven by a 3.3v 17 ? lvcmos driver. an optional 3-pole filter can also be used for additional spur reduction. it is recommended that the loop filter components be laid out for the 3-pole option. this will also allow the 2-pole filter to be used. for the lvcmos output, a termination example is shown in this schematic. for more termination approaches, please refer to the lvcmos termination application note. figure 3. ICS810001-21 schematic example u1 810001-21 schematic lf1 1 lf0 2 iset 3 vdd 4 nbp0 5 gnd 6 clk_sel 7 clk1 8 clk0 9 v0 10 vdd 11 mr 12 mf 13 v1 14 v2 15 v3 16 vdda 17 vddo 18 q 19 gnd 20 oe 21 nbp1 22 n1 23 n0 24 32 vddx 31 xtal_in0 30 xtal_out0 29 gnd 28 xtal_in1 27 xtal_out1 26 xtal_sel vdd 25 12pf 12pf c8 .01uf x1 vdd set logic input to '0' to logic input pins logic control input examples to logic input pins set logic input to '1' ru2 not install ru1 1k rd2 1k rd1 not install vdd vdd mr c ont rol vdda x2 pin25 r6 tbd cp2 tbd cp1 tbd rs1 tbd cs1 tbd lf1 3-pole loop filter example - (optional) lf0 vdd q1 driv er_lvcmos q2 driv er_lvcmos rs 150k r1 33 r2 33 pin18 pin11 pin4 rset 2.21k tl2 zo = 50 tl1 zo = 50 c5 .01uf vdd 2-pole loop filter c10 .01uf c9 10uf r3 10 vdd c1spare c2spare c3 spare c4 spare cs .22uf cp .001uf c6 .01uf vddx c12 .01uf c11 10uf r4 10 c7 .01uf vdd vddx vdd vdda vdd r5 33 tl3 zo = 50 receiv er
ics810001dk-21 revision b april 13, 2010 14 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll vcxo-pll e xternal c omponents choosing the correct external components and having a proper printed circuit board (pcb) layout is a key task for quality operation of the vcxo-pll. in choosing a crystal, special precaution must be taken with the package and load capacitance (c l ). in addition, frequency, accuracy and temperature range must also be considered. since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like hc49 be used. generally, a metal-canned package has a larger pulling range than a surface mounted device (smd). for crystal selection information, refer to the vcxo crystal selection application note. the crystal?s load capacitance c l characteristic determines its resonating frequency and is closely related to the vcxo tuning range. the total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, ic package lead capacitance, internal varactor capacitance and any installed tuning capacitors (c tune ). if the crystal c l is greater than the total external capacitance, the vcxo will oscillate at a higher frequency than the crystal specification. if the crystal c l is lower than the total external capacitance, the vcxo will oscillate at a lower frequency than the crystal specification. in either case, the absolute tuning range is reduced. the correct value of c l is dependant on the characteristics of the vcxo. the recommended c l in the crystal parameter table balances the tuning range by centering the tuning curve. the frequency of oscillation in the third overtone mode is not necessarily at exactly three times the fundamental frequency. the mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental. the oscillator circuit may excite both the fundamental and overtone modes simultaneously. this will cause a nonlinearity in the tuning curve. this potential problem is why vcxo crystals are required to be tested for absence of any activity inside a 200ppm window at three times the fundamental frequency. refer to f l_3ovt and f l_3ovt_spurs in the crystal characteristics table. the crystal and external loop filter components should be kept as close as possible to the device. loop filter and crystal traces should be kept short and separated from each other. other signal traces should be kept separate and not run underneath the device, loop filter or crystal components. vcxo characteristics table vcxo-pll loop bandwidth selection table lf0 lf1 iset xtal_in xtal_out r s c s c p r set c tune c tune 19.44mhz symbol parameter typical units k vcxo vcxo gain 6.6 khz/v c v_low low varactor capacitance 15 pf c v_high high varactor capacitance 29 pf bandwidth crystal frequency (mhz) m r s (k ? )c s (f) c p (f) r set (k ? ) 6hz (low) 27 4004 175 4.7 0.01 8.0 80hz (mid) 27 1000 150 0.22 0.001 2.21 475hz (high) 27 92 125 0.1 0.0001 3.3
ics810001dk-21 revision b april 13, 2010 15 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll crystal characteristics reliability information table 6. ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for ICS810001-21 is: 9365 symbol parameter test conditions minimum typical maximum units mode of oscill ation fundamental f n frequency 27 mhz 26.973 mhz f t frequency tolerance 20 ppm f s frequency stability 20 ppm operating temperature range 0 70 0 c c l load capacitance 12 pf c o shunt capacitance 4 pf c o / c 1 pullability ratio 220 240 f l_3ovt 3 rd overtone f l 200 ppm f l_3ovt_spurs 3 rd overtone f l spurs 200 ppm esr equivalent series resistance 20 ? drive level 1mw aging @ 25 0 c 3 per year ppm ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29c/w
ics810001dk-21 revision b april 13, 2010 16 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll package outline and package dimensions package outline - k suffix for 32 lead vfqfn table 7. package dimensions reference document: jede c publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 7. to p view indexarea d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n&n even n e d2 2 d2 (ref.) n&n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil singulation n-1 n chamfer 1 2 n-1 1 2 n radius n-1 1 2 n aa dd cc bb 4 4 4 4 4 4 bottom view w/type b id bottom view w/type c id bottom view w/type a id there are 3 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type b: dummy pad between pin 1 and n. 3. type c: mouse bite on the paddle (near pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ics810001dk-21 revision b april 13, 2010 17 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 810001dk-21 ics10001d21 32 lead vfqfn tray 0 c to 70 c 810001dk-21t ics10001d21 32 lead vfqfn 2500 tape & reel 0 c to 70 c 810001dk-21lf ics0001d21l ?lead-free? 32 lead vfqfn tray 0 c to 70 c 810001dk-21lft ics0001d21l ?lead-free? 32 lead vfqfn 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ics810001dk-21 revision b april 13, 2010 18 ?2010 integrated device technology, inc. ICS810001-21 data sheet femtoclock? dual vcxo video pll revision history sheet rev table page description of change date b t4b 8 10 14 15 16 lvcmos dc characteristics ta ble - corrected typo in v ih row from 3v min. to 2v min. parameter measurement information - updated 3.3v load ac test circuit diagram. replaced 4th paragraph in vcxo-pll external components section. crystal characteristics table - added 3rd overtone specs. updated vfqfn package outline. updated datasheet header/footer. 4/13/10
ICS810001-21 data sheet femtoclock? dual vcxo video pll disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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	To Download ICS810001-21 Datasheet File
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